20th IEEE International Conference on
Emerging Technologies and
Factory Automation

September 8-11, 2015, Luxembourg

News

Final Program Track 2 - Industrial Communication Technologies and Systems

 
T2.1: Wireless and Powerline Communication
Time: Wednesday, 09. Sept., 16:00 - 18:00
Chairs: Stig Petersen, Uwe Meier; Room: Hollenfels
16:00 - 16.20 Maryam Vahabi, Stefano Tennina, Eduardo Tovar and Bjorn Andersson
(202) Response Time Analysis of Slotted WiDOM in Noisy Wireless Channels
16:20 - 16:40 Federico Tramarin, Stefano Vitturi and Michele Luvisotto
(230) Improved Rate Adaptation Strategies for Real-Time Industrial IEEE 802.11n WLANs
16:40 - 17:00 Duc Khai Lam, Keishi Yamaguchi, Yasuhiro Shinozaki, Satoshi Morita, Yuhei Nagao, Masayuki Kurosaki and Hiroshi Ochi
(64) A Fast Industrial WLAN Protocol and its MAC Implementation for Factory Communication Systems
17:00 - 17:20 Gaetano Patti, Giuliana Alderisi and Lucia Lo Bello
(187) SchedWiFi: An Innovative Approach to support Scheduled Traffic in Ad-hoc Industrial IEEE 802.11 networks
17:20 - 17:40 Francisco Nombela, Enrique García, Jesús Ureña, Álvaro Hernández and Pablo Poudereux
(23) Robust Synchronization Algorithm for Broadband PLC based on Wavelet-OFDM
17:40 - 18:00 Pablo Poudereux, Raúl Mateos, Álvaro Hernández, Francisco Nombela and Fernando Cruz-Roldán
(24) Study of Suitable Filter Architectures for FBMC Techniques Applied to PLC Communications

 

T2.2: Industrial Ethernet
Time: Thursday, 10. Sept., 08:30 - 10:30
Chairs: Stig Petersen, Stefano Scanzio; Room: Wiltz
08:30 - 08:50 Uwe Hentschel, Marvin Elz and Steffen Bernet
(77) Automatic Device Scans in EtherCAT Networks with Cable Redundancy
08:50 - 09:10 Peter Danielis, Vlado Altmann, Jan Skodzik, Eike Bjoern Schweissguth, Frank Golatowksi and Dirk Timmermann
(52) Emulation of SDN-Supported Automation Networks
09:10 - 09:30 Long Qian, Zihan Chen and Peter Kazanzides
(249) An Ethernet to FireWire Bridge for Real-Time Control of the da Vinci Research Kit (dVRK)
09:30 - 09:50 Pavel Burget, Ondrej Fiala and Jan Prasek
(252) Simulation, modelling and delay estimation in Profinet networks
09:50 - 10:10 Artemios Voyiatzis, Konstantinos Katsigiannis and Stavros Koubias
(10) A Modbus/TCP Fuzzer for Internetworked Industrial Systems
10:10 - 10.30 Tatsuya Maruyama and Tsutomu Yamada
(129) Communication Architecture of EtherCAT Master for High-Speed and IT-enabled Real-Time Systems

 

T2.3: Clock and Network Synchronization
Time: Thursday, 10. Sept., 14:30 - 15:30
Chairs: Stig Petersen, Lucia Lo Bello; Room: Vianden
14:30 - 14:50 Gianluca Cena, Stefano Scanzio and Adriano Valenzano
(189) Reliable Comparison of Clock Discipline Algorithms for Time Synchronization Protocols
14:50 - 15:10 Aboubacar Diarra, Armin Zimmermann, Andreas Grzemba, Thomas Hogenmueller and Umair Asrar Khan
(117) Improved Clock Synchronization Start-Up Time for Switched Ethernet-Based In-Vehicle Networks
15:10 - 15:30 Linus Thrybom, Thanikesavan Sivanthi and Yvonne-Anne Pignolet
(164) Performance Analysis of Process Bus Communication in a Central Synchrocheck Application
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